Development and implementation of an integrated control system for devices in the area Supervisor: , Anastasios Ntagiouklas
Developing team: 11;12; Summary
The goal of the thesis is the implementation of a device which will properly receive and process voice commands to be sent via a local Ethernet network to a central PC of the house, which will then control several devices getting use of appropriately developed software. In summary, the first part of the thesis includes the research on appropriate components required for the implementation of the circuit (microphone, preamplifier, ADC – Analog-to-Digital Converter, FPGA – Field Programmable Gate Array), and their proper interconnection. The appropriate processing of the signal on the FPGA will result in building well-structured IP packets, which will be sent via Ethernet. The second part of the thesis consists of developing appropriate software which will receive the packets and recognize the voice commands using SAPI – Speech Application Programming Interface of Microsoft. After recognizing the commands, a control board with eight relays will be driven via the serial port.
High level desing of IEEE 802.11 physical layer using ImpulseC and implementation on FPGAs. Supervisor:
Developing team: 10; Summary
The purpose of this thesis is to design the physical layer of IEEE 802.11 protocol using ImpulseC and associated tools. ImpulseC based design will lead to automatic VHDL code generation for implementation in FPGAs.
Efficient FPGA Implementations of Synchronous Hash Functions Supervisor:
Developing team: 13; Summary
Cryptography algorithms are used in the telecommunications to protect the transmitted data. There are many types of the cryptography algorithms Symmetric ciphers, Asymmetric ciphers and Hash functions. Hash functions are used in digital signature, data integrity and message or user authentication. In FPGA implementations there are many design issues like the covered area, the power consumption and the time performance. The basic problem is a FPGA implementation with optimum tradeoff between cost and performance. So, the need for a hardware implementation with minimum covered area and low level of power consumption for a given time performance, is mandatory. In this diploma thesis FPGA implementations of synchronous hash functions are considered. Also, the above design issues are studied and used.
Design and Implementation using OpenCV liblary and acceleration using specialized hardware units Supervisor:
Developing team: 14; Summary
The main goal of this thesis is to develop an application for visual perception using OpenCV library. The library will be used for counting the time spent by CPU at various functions. Thesis will propose an appropriate code layring so that the specific functions will be able to be trasnferred below hardware abstraction layer and will implement part of the functions using existing hardware for smart cameras.